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  1. SystemDS
  2. SYSTEMDS-2050

Prints show in reverse order of merge of statement blocks

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Details

    • Bug
    • Status: Closed
    • Major
    • Resolution: Fixed
    • None
    • SystemML 1.1
    • None
    • None

    Description

      As pointed out by dusenberrymw - prints currently show up in reverse order after the merge of sequences of statement blocks. For instance, the following example

      print("test1");
      print("test"+2);
      print("test"+3);
      if(1==1){} 
      print("test4");
      print("test"+5);
      

      currently produces the following output

      test4
      test5
      test1
      test2
      test3
      

      The new instruction scheduling introduced with SYSTEMML-2039 ensures (as a byproduct) that prints within one DAG are scheduled in their original order. However, after the merge of statement blocks, prints without data dependencies can be reordered.

      This task aims to simply sort all DAG output instructions accordingly to their line numbers. Note that his only affects the new instruction scheduling as used for spark, hybrid_spark, and singlenode.

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              mboehm7 Matthias Boehm
              mboehm7 Matthias Boehm
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                Updated:
                Resolved: